Ashutosh Chakraborty

Brief Biography:

I am Ashutosh Chakraborty: image on the right side of this section is mine.  I am pursuing my PhD Degree (since August 2006) at the UT VLSI Design Automation Laboratory in Department of Electrical and Computer Engineering at the University of Texas at Austin.  My advisor is  Professor David Z Pan.  My reseach at UT is focussed on VLSI Physical Design for Manufacturability.

From September 2004 to June 2006, I worked as Research Assistant with the EDA Group in the Department of Computer Science at Politecnico di Torino, Italy.  My advisor there was Prof. Enrico Macii.  From August 2002 to August 2004, I worked as a Senior Member, Technical Staff with Mentor Graphics Corporation on their hardware verification and netlist optimization products.  I received a Bachelor of Tecnology (B-Tech) from the Department of Electrical Engineering (with best thesis award) at the Indian Institute of Technology, Delhi in 2002.

Contact Info:

Resume:

Projects:

• Double Edge Triggered Flip Flop Design - Undergraduate thesis  (2002) (See details)
• Induction motor current characterization - Undergraduate class project (2001) 
• Hardware emulation front-end with QT - Done during my job (2003) 
• Supporting user defined primitives in verilog compiler - Done during job (2004) 
• LCD Bus Power minimization using encodings - Done at Polito (2005) (See details)
• Regularity extraction and preservation during logic synthesis - Done at Polito (2005) (See details)
• Thermal resilient clock tree design - Done at Polito (2005) (See details)
• Circuit techniques for Leakage power minimization (2006) (See details)
• Dynamically Tunable Buffered Clock Tree design - Done at Polito (2006) (See details)
• Exploiting cross channel correlation on LCD buses for low power - Done at Polito (2006) (See details)
• Congestion aware router design using ILP and successive congestion relaxation - Done at UT (2006)
• Applying CNF SAT to global routing problem - (Course Project) Done at UT (2006)
• On Optimal Selection of Vth values for power minimization (Course Project) Done at UT (2006)
• NBTI Aware clock tree skew analysis and optimization - Done at UT (2007)
• Layout level timing optimization using active area perturbation of strained silicon - Done at UT (2007)

Links of Interest:

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