A 4-Channel Time-Interleaved ADC with Digital Calibration of Interchannel Timing and Memory Errors

Seminar
Tuesday, August 10, 2010
7:00 PM
Free and open to the public

An 11-b 160-MS/s 4-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-µm CMOS process is describe. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 dB to 62 dB after calibration with a 8.7 MHz input. The spurious-free-dynamic-range is increased from 47 dB to 78 dB.

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Speaker

Stephen H. Lewis

Professor
University of California, Davis