An 11-b 160-MS/s 4-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-Âµm CMOS process is describe. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 dB to 62 dB after calibration with a 8.7 MHz input. The spurious-free-dynamic-range is increased from 47 dB to 78 dB.
Tuesday, August 10, 2010
Free and open to the public