Application of Statistical Optimization for Process and Defect Tolerant Nanometer Scale Circuit Design

Tuesday, March 02, 2010
6:00 PM
Free and open to the public

The technology scaling is helping to achieve higher integration density and frequency in each technology generation. However, at the same time there is an increasing unpredictability in the physical properties of semiconductor devices because of lack of manufacturing control. The future nanodevices are predicted to have even higher variability and defects due to manufacturing limitations. This necessitates a tighter integration of process and design flows. Due to statistical nature of the process variation, we must deal with statistical design methodology since developing such a methodology can reduce the impact of yield loss incurred due to high variability.

A major challenge is to develop efficient parametric yield optimization algorithms at different levels of abstraction in the design flow. In order to address this problem, my work has mainly focused on developing efficient tractable approximations that can be employed to overcome the high computational complexity of the statistical problem that are encountered during logic synthesis, post-synthesis optimization, circuit timing prediction and robust memory design.

In this talk, I will give a brief overview of my work in these areas. I will cover in details, the methods for yield constrained power optimization using joint design time and post-silicon tuning methods for logic and SRAM. I will also discuss the challenges associated with defect tolerance in future nanotechnologies and in particular a defect tolerant CMOS-CNT (Carbon Nano Tube) architecture using novel coding of Boolean functions.

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Ashish Singh

Postdoctoral Researcher