Despite the end of Moore’s Law on the horizon, there is no end in sight to the rapid growth in the volume of data and applications to make use of it. To use that data, it must be stored, accessed, and moved, and this communication is often more demanding than the computation on that data. Worse yet, inefficient communication can leave a system woefully underutilized, which increases costs to the point of limiting the amount of data that can be practically processed.
In this talk, I describe techniques to improve communication efficiency, which in turn can improve performance, save energy, or even reduce manufacturing costs. First, I demonstrate how to best exploit the technology advantages of silicon photonics to design efficient interconnect architectures. Next, I show the benefit of optimizing communication with a vertically-integrated approach that considers the needs of algorithms while simultaneously appreciating the capabilities of the underlying hardware. In particular, I diagnose communication bottlenecks for graph algorithms on current hardware and develop optimizations to ameliorate those bottlenecks. Finally, I conclude by discussing the importance of novel hardware architectures to achieve efficient communication.