Architectural Tradeoffs in Designing NVM based LLC

Tuesday, October 02, 2018
3:30 PM to 4:30 PM
ECJ 1.312
Free and open to the public

First I will talk about our recent work on incorporating Non-volatile Memory (NVM) as Last Level Cache (LLC). I will highlight different tradeoffs (e.g. NVM latency vs capacity vs reliability) involved in designing such NVM based LLC and further discuss our solutions. In the end, I will go over some of the focus areas of our research Lab (Parallel Computing Lab) as well as some recent research directions.


Ishwar Bhati

Research Scientist
Intel Labs India

Dr. Ishwar Bhati is a Research Scientist in Parallel Computing Lab (PCL) at Intel Labs India. He received his Bachelor of Technology (BTech) in Electronics and Communication Engineering from Indian Institute of Technology (IIT) Guwahati in 2005 and his Ph.D. in Computer Engineering from University of Maryland, College Park in 2014 under Prof. Bruce Jacob. He currently works on the system architecture suited for emerging applications with a focus on Machine and Deep Learning. Prior to Intel, he worked in Oracle, LSI Logic, Nevis Networks, and ST Microelectronics, designing and architecting complex hardware chips. More detailed about Dr. Bhati can be found at his website: