Asynchronous SAR ADC: Past, Present and Beyond

Seminar
Wednesday, February 17, 2016
12:00 PM to 1:00 PM
MEZ 1.306
Free and open to the public

The demand of low-power and high-speed ADC has been escalating in the past decade due to emerging low-power applications with wide bandwidth requirement, including both wireless and wireline systems. Historically, the ADC in this targeted specification regime has been dominated by Flash topology, where all the level comparisons are accomplished in parallel. However, the associated complexity prevents it from a true low-power solution. About a decade ago, the asynchronous successive approximation (SAR) architecture was proposed to minimize the overall converter complexity while improving the speed of the binary search algorithm. The first proof-of-concept silicon prototype in 130nm CMOS achieved the order-of-magnitude improvement in power efficiency. Since then, this low power ADC architecture has been widely adopted for various power-constraint, high-speed, medium to high resolution applications, such as the recently published 90GS/s ADC.  In this tutorial talk, we will review the evolution of this ADC architecture, including the recent trend and potential extensions. The related design issues of such ADC architecture will also be examined in this talk.

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Speaker

Mike Shuo-Wei Chen

Professor
University of Southern California

Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University in 1998, and the M.S. and Ph.D. degree from the University of California, Berkeley in 2002 and 2006, all in Electrical Engineering. As a graduate student, he proposed and demonstrated the asynchronous SAR ADC architecture, which has already been adopted today in industry. Since 2006, he has been working on mixed-signal and RF circuits for various wireless standards at Atheros communications (now Qualcomm-Atheros). He has been with the EE department at University of Southern California since 2011 and currently holds the Colleen and Roberto Padovani Early Career Chair position. His research group is having fun exploring the limit of analog mixed-signal, RF ICs, Bio-inspired electronics, and signal processing techniques for circuits and systems.

Dr. Chen received an honourable mention in the Asian Pacific Mathematics Olympiad, 1994. He was the recipient of the NSF Faculty Early Career Development (CAREER) Award and DARPA Young Faculty Award (YFA) in 2014, the UC Regents’ Fellowship at Berkeley in 2000, and Analog Devices Outstanding Student Award for recognition in IC design in 2006.