Energy-efficient computing remains a principal performance- and feasibility-limiting concern across the broad range of computing applications, from near and sub-threshold IoT systems to High-performance Computing. Independent advances in the areas of clocking (through low-power clock generation and distribution, gating) and voltage regulation (Dynamic Voltage and Frequency Scaling, Integrated Voltage Regulation) have been key enablers to efficiency improvements in digital SoCs over the past couple of decades.
The benefits achieved by these techniques have, in recent years, saturated somewhat. The historically unheralded problem of voltage margins required in real-world SoCs -- to address aging , temperature variation (especially in low-power systems), and supply noise in particular -- has emerged as a salient contributor to inefficiency, sparking various efforts to address this challenge.
In this talk, I identify the synergies between the traditionally independent systems of clock and power delivery, and make the case for a unification of these systems to address the efficiency challenge. Through a discussion of test-chip results, I will demonstrate the promise of this approach, and highlight the challenges in the way of employing the approach to altogether eliminate voltage margins in digital systems.