As CMOS scales to its physical limits with subwavelength lithography, it becomes increasingly challenging to fabricate integrated circuits with sufficient yield and affordable cost with improved performance. Below 65nm feature sizes, as well as beyond the life of CMOS, it becomes increasingly apparent that circuits must be constructed from simpler, more regular structures and geometry patterns than those presently used today. In this presentation we describe the use of regular logic and circuit fabrics for defining the underlying silicon geometries onto which scaled CMOS circuits should be mapped. While one might expect some area and performance penalty with such regularity enforcement, our work has found that with careful selection of the regular circuits and supporting design methodology, we can mitigate and ultimately eliminate such penalties. We will show implementation examples for digital, analog and RF circuits and technologies.
Monday, May 08, 2006
Free and open to the public