Coherent Large-Scale InP Photonic Integrated Circuits

Wednesday, November 02, 2011
7:00 PM
Free and open to the public

The extension of the electronic IC concept to photonics ICs was first proposed in the late 1960s. Since this time, photonic ICs (PICs) have been economically challenged to provide the same value proposition as electronic ICs, resulting in a substantially slower technology and product development rate, especially for devices employing active elements. This trend is shown in Fig. 1 which shows the scaling of data capacity per chip for InP-based transmitters utilized in commercial networks. In 2004, the introduction of commercial large-scale dense wavelength division multiplexed (DWDM) 100 Gb/s InP transmitters resulted in an order of magnitude increase in data capacity per chip by scaling the number if integrated functions by >10x. These devices exhibited both increased integration scaling within a given DWDM channel as well as integrating multiple (10) channels onto a single chip.

More recently, the adoption of higher spectral efficiency coding techniques and the scaling of total bandwidth has driven the integration density per chip by another order of magnitude, resulting in devices with >450 integrated functions per chip. This integration density has enabled the development of 500 Gb/s and 1 Tb/s coherent PM-QPSK (polarization-multiplexed quadrature phase shifting keying) multi-channel transmitter and receiver PICs that are subject of this talk. The large-scale monolithic integration provides significant reductions in the packing complexity, size, fiber coupling, and power consumption as well as improvements in reliability that offer significant benefits at both the component and system level and promise to enable the economic viability of next generation optical systems.

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Fred Kish

Vice President, PIC Development and Manufacturing
Infinera Corporation