Computational Capacity: Uses in Hardware-Software Codesign and Software Performance Enhancement

Seminar
Thursday, April 29, 2010
7:00 PM
Free and open to the public

Performance stability has long been a major parallel and sequential computing problem. Apparently small application changes on a given machine, or architectural changes for a given application, can yield surprisingly large performance changes. How can we improve the design process to produce systems with more predictable performance characteristics? The computational capacity model is designed to do this by fast design space exploration, using a wide representation of applications.

Large regions of the 3-D codesign space representing hardware (HW) cost (in terms of bandwidth and power), system performance, and SW load variation can be explored simultaneously via capacity-based codesign. The method is much faster than current simulation methods used for system design. Also, performance enhancement insight about when program transformations will help and by how much, can be derived from the model. Some results obtained from prototype implementations of this algebraic model will be presented.

We define Ci,j, the computational capacity of a computer HW node i, as the amount of the node's bandwidth used in computational phase j. Using HW parameters for a given system, together with corresponding measured Ci,j values for a collection of SW phases, a comprehensive codesign equation can be written. This equation can be used in HW design by holding SW capacity ratios invariant. By holding HW parameters invariant, capacity inequalities and the codesign equation can be used as a guide to performance enhancement for a set of applications.

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Speaker

David Kuck

Intel Fellow, Software and Services Group, and Director of the Parallel and Distributed Solutions Division
Intel