Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single die. However, scaling is facing several problems - severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. Hence, reliable, low-power designs require a shift in design paradigm. We believe that /device aware circuit and architecture design/ along with statistical design techniques can provide large improvement in power dissipation while providing the required reliability and yield. In this talk I will present device aware CMOS design to address power and reliability problems in scaled technologies for different application domains high-performance with power as constraint and ultra-low power with reasonable performance. Design techniques at different levels of abstraction (device, circuit, architecture) will be addressed. Different Si and possible non-Si device options will be considered for the nanoscale technology regime.
Thursday, April 20, 2006
Free and open to the public