There has been a resurgence of interest in asynchronous (i.e. clockless) digital design in recent years, as designers confront formidable challenges of high-speed clock distribution, chip complexity, power, design time, mixed-timing domains and reusability.
This talk is in two parts. First, I will give a brief overview of asynchronous and GALS (globally-asynchronous locally-synchronous) design,including a basic technical introduction and highlights of recent industry activity (Fulcrum Microsystems [now part of Intel], Boeing, Sun, Philips) andacademia. I will also survey some of my key research areas: (i) robust mixed-timing interfaces, (ii) low-power delay-insensitivecodes for global communication, and (iii) ultra-low energy systems (subthreshold/near-threshold).
In the second part, I will introduce our recent asynchronous switch design for very low-overhead GALS interconnection networks.Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems.However, they have found only limited applicability so far due to two main reasons: the lack of proper design tool flows as well astheir significant area footprint over their synchronous counterparts. This talk proposes a largely unexplored design point forasynchronous NoCs, relying on transition-signaling (i.e. 2-phase handshaking) and single-rail bundled data encoding, which contributesto break the above barriers.
Compared to a leading lightweight synchronous switch architecture, "xpipesLite," the post-layout asynchronous switch achieved a71% area reduction, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit.A semi-automated CAD tool flow was developed, using Synopsys Design Compiler and IC Compiler.
This is joint work with Davide Bertozzi and Alberto Ghiribaldi(University of Ferrara, Italy).