This talk presents a pipelined ADC IC and a reconfigurable voltage-controlled oscillator (VCO) based ADC IC, both of which are enabled by a new digital background calibration technique that cancels nonlinear distortion. The pipelined ADC IC achieves a peak SNR of 70dB and a −1 dBFS SFDR of 85 dB at a sample-rate of 100MHz. It is implemented in a 90nm CMOS process and consumes 130mW from 1.2V and 1.0V analog and digital power supplies, respectively. The VCO based ADC has the functionality of a reconfigurable continuous-time delta-sigma modulator, but unlike a conventional delta-sigma modulator it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses much less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The IC is implemented in 65nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07mm2.
Tuesday, May 03, 2011
Free and open to the public