Future Computing Architectures: Challenges and Opportunities

Wednesday, January 30, 2019
12:00 PM to 1:00 PM
EER 1.518
Free and open to the public

This talk will cover some key issues that we consider critical to solve in modern and future computing platforms. Our focus will especially be on the issues related to the memory system and data access, critical bottlenecks in both high-performance and energy-constrained computing platforms of today. We will show how the memory system greatly affects all key metrics we care about today, including security, reliability, performance, energy efficiency, predictability, and the enablement of key new applications. This importance arises from critical technology scaling issues at the circuit and device layers as well as greatly increasing demand for data and its fast and efficient analysis at the system and software layers.

Some key issues we expect to touch on, at different levels of detail, are:

1) designing fundamentally secure, reliable, safe architectures, motivated with real-world examples including the widespread RowHammer vulnerability present in modern DRAM chips,

2) enabling data-centric and hence fundamentally energy-efficient and sustainable architectures that are capable of performing computation near where data is stored,

3) fundamentally reducing both energy consumption and latency by exploiting heterogeneity that is widespread in both hardware and software, and

4) designing fundamentally-efficient architectures for genomics/medicine/health via hardware/software cooperation. We will focus on both problems and new solution directions and discuss how we can overcome the fixed mindsets in solving key challenges in future computing architectures. The problems and solutions we will examine span across levels of transformation in computing, all the way from hardware devices to software algorithms.

We will show that careful solutions that span across the levels can lead to orders of magnitude improvements in efficiency and performance, and derive guiding cross-layer principles for the design of future computing architectures.


Onur Mutlu

Onur Mutlu

ETH Zurich

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.