The regenerative comparator is at the heart of A/D converters and digital communication receivers. It senses the memory cell in SRAM and DRAM.
Since the circuit is unstable and always operates with large signal swings that drive transistors to the extreme, so far there is no well-known method for a quantitative analysis of the circuit.
I will show that by exploiting circuit symmetry, its dynamics can be fully visualized in the phase plane defined by the circuit’s two orthogonal modes. From this follow decompositions into simple equivalent circuits for each mode, and they show how static and dynamic offsets arise from transistor and load unbalance. At low supply voltages, the offset and noise in the comparator can become the bottleneck to system performance.