Hardware Specialization for Efficiency and Performance

Seminar
Monday, March 09, 2020
10:30 AM to 11:30 AM
EER 3.646
Free and open to the public

With the demise of Dennard scaling and the slowing of Moore’s Law, hardware specialization is one of very few ways to improve energy efficiency and/or performance. The standard way to specialize is to add dedicated accelerators implemented as on-die fixed function circuits that are orders of magnitude more computationally efficient than standard processors. Those accelerators could be connected to the rest of the system through a network-on-chip or integrated into an application specific processor (ASP) that has further data path and/or memory system optimizations. Such approaches are often referred to as Application-Specific Integrated Circuits (ASIC).

In this talk, I will discuss an alternative hardware specialization based on reconfigurable logic as is found in field programmable gate arrays (FPGAs). Conventional wisdom says that FPGAs are an order of magnitude less power efficient, an order of magnitude less performant, and an order of magnitude larger than ASICs, as well as being harder to program. When analyzed in a full system context, however, FPGAs are significantly better than the conventional wisdom and, in some cases, are more efficient than ASIC alternatives. When combined with their other advantages such as dynamic reconfigurability and wide applicability, FPGAs are far more compelling than previously thought even at cloud-scale volumes. I will describe why the conventional wisdom should be reexamined, give examples of novel uses and cloud deployments of FPGAs, and describe how FPGAs could be made easier to program.

Speaker

Derek Chiou

Derek Chiou

Partner Architect
Microsoft

Derek Chiou is a Partner Architect at Microsoft where he leads the Azure Cloud Silicon team working on FPGAs and ASICs for data center applications and infrastructure, and a researcher in the Electrical and Computer Engineering Department at The University of Texas at Austin.  Until 2016, he was an associate professor at UT.  His research areas are novel uses of FPGAs, high performance computer simulation, rapid system design, computer architecture, parallel computing, Internet router architecture, and network processors.  Before going to UT, Dr. Chiou was a system architect and lead the performance modeling team at Avici Systems, a manufacturer of terabit core routers. Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT.