Idempotent Processing

Seminar
Monday, April 02, 2012
7:00 PM
Free and open to the public

With energy efficiency and device reliability becoming primary constraints rather than energy, revisiting processor design principles can be useful and interesting. In this talk, I will present a processing paradigm called Idempotent Processing, we have developed that targets speculation recovery and reliability.

I will first introduce the concept of application idempotence i.e. programs naturally decompose into a continuous set of regions, where each region can be re-executed to produce the same result. This natural property in programs provides a way to handle reliability, fault-recovery, and speculation-recovery using the single mechanism of re-execution. I will describe a compiler framework that can automatically identify such regions - this problem has some direct connections to graph analysis and vertex mincut. Using such a compiler, we develop the Idempotent Processor Architecture, whose primitive execution block is an idempotent code region. With the capability of recovery by simply re-executing, an Idempotent Processor design executes efficiently and correctly under various constraints, including faulty hardware, control mis-speculation, out-of-order retirement, precise exceptions etc. all while avoiding energy-consuming hardware support like checkpoints, re-order buffer, load-store queues etc. I will show three specific case-studies: an in-order processor designed exploiting idempotence, hardware-transient fault recovery exploiting idempotence, and finally adding demand-paged virtual memory and speculation support to GPUs.

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Speaker

Karu Sankaralingam

Assistant Professor
University of Wisconsin-Madison