IEEE Distinguished Lecture: IC Technology at New Nodes Made Easy

Wednesday, December 04, 2013
6:00 PM
POB 2.402
Free and open to the public

Despite increasing economic and technical challenges to scale CMOS, we continue to witness unprecedented performance with 22-nm fully-depleted tri-gate devices now well in production. This tutorial seminar offers a summary of how CMOS device technology has progressed over the past two decades. We will review MOS device and short-channel fundamentals to motivate how device architectures in production have evolved to incorporate elements such as halos and spacers, mechanical strain engineering, high-K dielectric and metal gate, fully-depleted device architectures and finally, tri-gate finFETs.

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Alvin Loke


Alvin Loke received his BASc degree from University of BC, and MS and PhD degrees from Stanford. His doctoral work focused on copper interconnects with low-K polymer dielectrics. From 1998 to 2001, heworked on CMOS technology integration at HP Labs and then at Chartered Semiconductor Manufacturing as an Agilent assignee. In 2001, he transferred to Fort Collins, Colorado where he designed CMOS PLL circuits for embedded SerDes and ASIC clocking. From 2006 to 2013, he was with Advanced Micro Devices where he designed high-speed electrical/optical link circuits and addressed analog/mixed-signal concerns for next-generation CMOS. He recently joined Qualcomm where he works on mobile IO links. Alvin has authored 40 publications and holds 14 US patents. He served on the CICC technical program committee and as Guest Editor of the IEEE Journal of Solid-State Circuits. He was an active SSCS chapter officer in Fort Collins for 10 years.