In order for the computing industry to strive and fuel human innovation, usable computation must continue to become faster and cheaper. The traditional approach of waiting for sequential processor performance to increase has broken down due to power constraints, design complexity, and techniques such as pipelining running out of steam. As a response to these problems, computer architects have turned to parallelism in the form of multicore and manycore processors where tens, hundreds, or even thousands of processor cores are being integrated onto a single chip. The design of these multicore processors and the architectural mechanisms needed to make them scale and provide usable performance to the average programmer will be key to driving the computing industry.
This talk introduces two new architectural mechanisms which enable applications to utilize scalable multicore processors by solving the questions of how to protect multiple disparate systems being integrated onto a multicore processor and how to manage memory locality on a multicore processor.
This talk will describe Configurable Fine-Grain Protection (CFP) which enables multicore virtualization thereby allowing multiple operating systems with different architectural requirements to share a single multicore processor while guaranteeing both isolation and performance independence. Also, Remote Store Programming (RSP) which is composed of hardware and software mechanisms will be presented which enables multicore programs to carefully control communication costs while still using familiar shared memory programming. All of the presented techniques will be discussed in the context of three real world systems: The 16-core MIT Raw Processor, the 64-core Tilera TILE64 Processor, and the MIT Factored Operating System (fos), a scalable operating system for future multicores and cloud systems.