Memory Systems for Multiprocessors: AMD Opteron Memory Coherence and Consistency

Thursday, November 18, 2004
6:00 PM
Free and open to the public

In this talk we will give brief background on the difference between memory coherence models (more commonly referred to as "cache coherence protocols") and memory consistency models and emphasize that, while the two are in many ways inter-related, they should be logically separated in the minds of microprocessor designers. We will then discuss how the AMD Opteron coherence protocol (using HyperTransport, and Direct Connect Architecture) works for some common memory transaction types.

We will then switch to the topic of memory consistency, discussing common memory consistency models, describing the differences between them, and detailing the most common memory model in x86 processors (normally called "processor consistency").

We will conclude with a discussion of why the AMD Opteron coherence protocol is unique and describe how this uniqueness leads to both improved performance against more conventional topologies for multiprocessors of small/medium scale (2 to 8 processors) and also provides new possibilities for optimization of cache coherent multiprocessors.

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Kevin Lepak