Predictable MPSoC Stream Processing Using Invasive Computing

Monday, June 06, 2016
10:30 AM to 11:30 AM
POB 2.402
Free and open to the public

Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds.  Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource (e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional variations and jitter in execution time.  This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems. 

Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and inflexibility. 

In this talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions.  Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing. In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In Invasive Computing, isolation is supported on all levels of hardware and software including the OS.  Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.

For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.


Jürgen Teich

Friedrich-Alexander-Universität Erlangen-Nürnberg

Jürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, where he is directing the Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors) from the University of Kaiserslautern, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude) from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and Communications Networks Laboratory (TIK), ETH Zurich, Switzerland with his Habilitation on the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996. From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology Department, University of Paderborn, Germany.

His current research focuses on electronic design automation of embedded systems with emphasis on hardware/software co-design, reconfigurable computing and multi-core systems.
Prof. Teich has organized various ACM/IEEE conferences/symposia as Program Chair including CODES+ISSS´07, FPL´08, ASAP´10, and DATE´16.  He serves regularly as a TPC member of many program committees including DAC, ASP-DAC, ICCAD, FPL, ASAP, FPT, FPGA, RECONFIG, ESTIMEDIA, VLSI Design, GECCO, EMO, RTSS, etc.  He also serves in the editorial board of journals including ACM TODAES and JES and has edited two text books on Hardware/Software Co-Design (Springer).

Prof. Teich received numerous best paper awards including a Paper Award of HiPEAC at the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM´10), and at ACM/EDAC/IEEE Design Automation Conference (DAC´14), the 24th IEEE International Conference on Application-specific Systems, Architectures and 
Processors (ASAP´14) Best Paper Award and the NASA/ESA Conference on Adaptive Hardware and Systems (AHS´2015) Best Paper Award. Also, he received the P.K. McElroy and R.A. Evans Award for the best paper at the 60th Annual Reliability and Maintainability Symposium (RAMS´14) and the Best Paper Award of the International Conference on Field-Programmable Technology (ICFPT´07).

Prof. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.  From 2003-2009, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG) for the area of Computer Architecture and Embedded Systems. He has been the initiator and coordinator of the DFG priority programme 1148 on "Reconfigurable Computing". Since 2010, he has also been the principal coordinator of the Transregional Research Center 89 "Invasive Computing" funded by the German Research Foundation (DFG).  In 2011, he was elected member of the Academia Europaea