Traditionally, the physical layers of wireless communication protocols are implemented with fixed function ASICs. With rapid growth in the number and the complexity of wireless protocols, it has become increasingly difficult for these hard-wired ASICs solutions to adapt. Software Defined Radio (SDR) promises to deliver a cost effective and flexible solution by implementing the wide variety of the wireless protocols in software. However, the computational requirements of current generation wireless communication protocols are orders of magnitude higher than the capabilities of modern programmable processors. A wireless protocol processor must sustain this high computation throughput while operating under the tight power budget of an embedded mobile device. The combination of the steep performance and power requirements has so far prevented SDR solutions from being commercialized.
In this talk, I will present SODA, a multi-core DSP processor architecture that meets both the performance and power requirements for current generation wireless protocols. SODA consists of one general purpose control processor and four high-performance data processors. Each data processor consists of a 32-lane Single-Instruction Multiple-Data (SIMD) execution engine that is optimized for wireless protocols. In addition to processor design, I will also present our work on algorithm optimizations, programming language design, and compilation support for the SODA processor.