As CMOS scales to its physical limits with subwavelength lithography, it becomes increasingly challenging to fabricate devices and interconnect such that the resulting integrated circuits have: acceptable performance, control of variations, sufficient yield and affordable cost. Below 65nm feature sizes, as well as beyond the life of CMOS, it becomes increasingly apparent that circuits must be constructed from simpler, more regular structures and geometry patterns than those presently used today. In this presentation we describe the use of regular logic and circuit fabrics for defining the underlying silicon geometries onto which nanoscale CMOS circuits should be mapped. While one might expect some area and performance penalty with such regularity enforcement, our work has found that with careful selection of the regular logic circuits and supporting design methodology, we can mitigate such penalties. Moreover, by developing new methodologies and mapping algorithms to exploit the newfound manufacturability and predictability of regular circuits, it would appear that the performance of regular logic can surpass that of seemingly more flexible logic cells.
As part of this presentation we describe a first-step toward a more general "regular logic brick" methodology, where a block design using logic bricks becomes analogous to a memory block design. We will show implementation comparisons with standard cells for several examples, including an embedded processor, and describe our ongoing work toward a complete regular logic brick design methodology. In addition, since the challenges for analog and RF design are even more pronounced in terms of control of variations, we will further describe a new methodology for robust design using regular analog and RF circuit fabrics. Several examples will highlight the importance of statistical design methods for analog and RF circuits in nanoscale technologies.