Bi-directional Brain Computer Interfaces (BBCI), systems capable of recording from, and providing stimulus to the nervous system offer great promise for helping patients with motor defects, and serve as a critical tool for the understanding of the Brain. It is anticipated that future BBCI systems will require processing over a thousand channels between stimulus and recording, while maintaining power, volume, and precision constraints.
Much progress has been made in recent years to advance the state-of-the-art in integration and power dissipation. However, existing methods, largely extensions of traditional approaches to Analog-Front-End (AFE) design do not scale well to the new thousand channel paradigm. Further, the problem of canceling artifacts of stimulation during recording are challenges-Significant improvement is required in differential artifact cancellation, and common mode cancellation remains an open problem.
In this talk, I will discuss recent work in my group focusing on circuit-architectures that address two key areas (1) scalability in frequency, channel-count and process-technology (2) Exploiting the signal statistics of neural signals to meet challenging system level performance ~(e.g. 14b ADC resolution) using much simpler, robust, low-power circuits. Silicon measurements of a 64-channel prototype in 65nm CMOS will be discussed.