As people cram more and more functions into IC chips, the chip power density quickly approaches its fundamental limit. Power has surpassed performance and become the number one concern in many chip designs, from mobile to server applications. This talk will present some recent works on how to improve chip power efficiency at both architectural level and circuit level. At the architectural level, the power challenge is compounded by the increasingly large demand for on-chip communication bandwidth and data storage capacity. I will show how to efficiently monitor the performance of on-chip network and shared cache in chip multiprocessors. Dynamic voltage and frequency scaling control techniques for the shared resources will be described. At the circuit level, variability is another challenge that exacerbates the power problem. This talk will introduce a couple of voltage adaptation techniques that aim to harness the variability challenge in a power-efficient manner.
Wednesday, April 10, 2013
Free and open to the public