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Vivekananda M. Vedula, Adam T. Tate, Dr.
Raghuram S. Tupuri, and
Professor Jacob A. Abraham |
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Manufacturing test generation complexity for
state-of-the-art processors is very high |
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High cost |
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Increased time to market |
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Need at-speed test to catch realistic defects |
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Can’t pay the area and performance overhead of
scan-based test in high-performance processors |
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Need to exploit the hierarchy in large designs |
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Translating tests for an embedded module to the
full-chip level is extremely difficult |
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Static analysis of control & data flow in a
program to derive a slice |
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Slice: the set of statements & variables
transitively relevant to the slicing criterion |
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Slicing criterion: a program point defined by a
statement or variable(s) in a statement |
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e.g. I/O signals of target module |
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Manipulate language semantics rather than
structural semantics |
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Implemented into a tool called FACTOR for
RT-level Verilog |
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Derive the constraint slice of a Module Under
Test (MUT) using Primary Input AccessiblE Registers (PIERs) as additional
pseudo-primary inputs/outputs |
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Synthesize to gate level and compose with MUT |
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Use a commercial sequential ATPG tool to
generate test patterns |
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Perform hierarchical slicing for large designs |
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Program slicing provides a method to reduce the
complexity of designs |
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The reduced designs allow a reduction in test
generation time, allowing faster time-to-market |
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Scalable to large designs; fits into design flow |
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Immense potential for other CAD applications |
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Notes