Research Review for Industry
Computer Architecture and VLSI/CAD Research Areas
Tues, Aug 28, 2007
Agenda
| 9:20am |
Welcome. Professor Anthony P. Ambler,
Chairman of ECE: ACE
2.302 |
| 9:30am |
Designing integrated systems for the next
generation of applications:
Professor Jacob Abraham |
| 10:20am |
Harnessing the next wave of process
technology improvements over the next decade: What will the
microprocessor look like?
Professor Yale Patt |
| 11:10am |
Coffee break - ACE
2.402 |
| 11:40am |
Dual tracks |
|
| |
Computer Architecture: ACE
2.302
1. Derek Chiou:
FPGA-Accelerated Simulation Technologies (FAST): An Overview
2. Dam Sunwoo:
FAST Functional Models
3. Nikhil Patil: FAST Timing Models
4. William Reinhart:
Abstracting Timing and Statistics in a Hardware Simulator
5. Hari Angepat: RAMP-White
|
VLSI/CAD: RLM
4.102
1. Nur Touba, Research in Test Compression and Error
Detection
2. Jacob Abraham, Self-Test of Embedded Systems
3. Shobha Vasudevan, High-Level Analysis for Reducing
Verification
Complexity,
4. Adnan Aziz, Reduced Models for Functional Verification
|
| 1:10pm |
Lunch - ACE Connector
Lobby |
|
| 2:10pm |
Dual tracks |
|
| |
Computer Architecture: ACE
2.302
1. Lizy John, LCA Research in Computer Architecture, Performance
Evaluation
and Workload Characterization
2. Ajay Joshi, Applying Workload Synthesis for Microprocessor
Performance
Evaluation
3. Lloyd Bircher, Complete System Power Measurement, Modeling and
Management
4. Ciji Isen, Embedded Java Workloads: Peeling through the layers
of execution
5. Dimitris Kaseridis, Performance analysis and exploration of
multiple
threads/cores using Sun UltraSPARC T1 (Niagara)"
|
VLSI/CAD: RLM
4.102
1. David Pan,
Nanometer IC Physical Design and Manufacturing Closure
2. Minsik Cho,
Model Based DFM Aware Routing
3. Michael Orshansky,
Statistical Design Methods for Power Reduction
and Yield Improvement
4. Murari Mani, Joint Design-Time and Post-Silicon Parametric
Yield
Optimization
|
| 3:30pm |
Break - RLM 4.102
Foyer |
|
| 3:50pm |
Dual tracks |
|
| |
Computer Architecture: ACE
2.302
1. Mattan Erez, Saving Power and Overcoming the von Neumann
Bottleneck with Hierarchical Bulk Operations
2. Moinuddin Qureshi, Adaptive Caching for High-Performance Memory
Systems
3. Francis Tseng, Braids: Out-of-order Performance with (almost)
In-Order Complexity
4. Aater Suleman, ACMP: An Architecture to Handle Amdahl's
Law
5. Jose Joao, Dynamic Predication of Indirect Jumps; removing a
performance bottleneck in Object-oriented code
|
VLSI/CAD: RLM
4.102
1. Shouli Yan,
Mixed Signal Integrated Circuits Research
2. Ranjit Gharpurey,
An Overview of Research in RF and High-Speed Analog Circuit
Design
3. Arjang Hassibi,
Integrated Biochips
4. Ramtilak Vemu,
Application-Level Fault Tolerance
|
| 5:15pm |
Wind-up - ACE
2.302 |
|
| 6:00pm |
Small dinner parties as desired |
|
