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The Massively Broadband Future

By Prof. Ted Rappaport with students Felix Gutierrez and James Murdock

Prof. Ted Rappaport envisions a future in which short-range, Giga-bit-per-second 60GHz wireless devices will completely revolutionize present-day media and data storage and transfer mechanisms, enabling wireless “information showers” to transfer massive amounts of information between devices in fractions of a second. The goal of our research is to create inexpensive, massively-wideband, fully-integrated wireless CMOS (Complementary Metal Oxide Semiconductor) communications technologies for operation at frequencies of 60 GHz and above. The applications for this research are numerous, and extend well beyond the realm of traditional wireless technologies.

The enormous amount of bandwidth available at frequencies of 60 GHz and above will allow consumers and enterprises to replace paper, magnetic, and wired media with inexpensive wireless devices, the implications of which are wide-ranging. Future generations of consumer electronics, through interaction with pre-installed wireless hubs and “information showers,” will allow users to stream high definition videos or download whole libraries of information in fractions of a second, rather than minutes or hours as with current technologies.

As another example, data center designers will be able to alter the architecture of computers and interconnections, using low power, high-speed wireless links to replace power-hungry cables. The massive data rates of 60 GHz wireless devices will allow computer designers to alter processing architectures, thereby isolating heat-intensive components for cooling and greatly reducing the carbon-footprints and cooling costs of large data centers. In addition, wireless, ad-hoc, high-quality video-surveillance systems, enabled through 60 GHz technologies, will enhance security for combat troops in urban environments.

Though the potential for 60 GHz communications is enormous, there are many challenges to overcome before the 60GHz vision becomes a reality. In order to make 60 GHz technologies as integrated and low-cost as possible, we are working on three broad sub-areas: on-chip antennas, 60 GHz circuits implemented in CMOS technologies, and improving knowledge of the 60 GHz wireless channel. Ultimately, Rappaport and his team envision their research in 60 GHz wireless technologies culminating in a completely integrated, on-chip transceiver prototype, and implementing an on-chip channel sounder suitable for portable use.

An efficient antenna must be roughly the size of the wavelength that corresponds to its operating frequency. An electromagnetic wave propagating through a silicon substrate has a wavelength of approximately 2.5 millimeters – comparable in size to a microchip. Together, these two facts make 60 GHz the first realm of wireless communications in which it is feasible to integrate the antenna directly on the chip that contains the rest of the transceiver, instead of keeping and interconnecting the antenna off-chip, as is done with today’s technologies. We are exploiting the small wavelength of 60 GHz and discovering the design rules needed to fabricate an on-chip antenna directly on a CMOS substrate, while striving to maximize efficiency, directionality, and gain. Developing these methods will allow companies to build fully integrated 60 GHz transceivers that – due to the low cost of CMOS semiconductor production – are extremely cheap to manufacture. We recently completed our first tape-out (i.e. design and production) of several on-chip antennas and are currently characterizing their performance. We will use what we learn from this and future studies to produce on-chip horizontally-printed antennas that do not lose substantial energy to the lossy CMOS silicon substrate, which will be necessary to achieve our goal of a high-gain directional on-chip antenna. Our research experience will also allow us to explore newer semiconductor processes and alternative approaches for making on-chip antennas and RFICs.

From a design point of view, CMOS is not ideal for the production of high-frequency devices that must process analog signals. However, CMOS has two advantages that ultimately make it the production-technology of choice for the 60 GHz future. First, CMOS is far superior to bipolar transistor technologies for purposes of digital integration, which is an important advantage if 60 GHz devices are to operate at extremely high data-rates that require substantial baseband processing and baseband control of analog circuits. Second, CMOS is far less expensive than other production technologies due to its ubiquitous use in today’s digital circuitry. These advantages motivate researching ways to make CMOS usable for the processing of analog signals in the 60 GHz range. Rappaport’s current focus is on the use of passive devices, primarily inductors and transmission lines, to resonate-out parasitic capacitances associated with CMOS transistors and to design matching circuits that allow for the complete integration of the transceiver onto a single chip. In addition, Rappaport’s team is beginning to look at the design and performance of active components, such as amplifiers and oscillators.

Another area of focus for Rappaport is improving channel models for 60 GHz devices. A wireless channel model describes how a signal transmitted at a particular frequency is dispersed on its way to the receiver. Good channel models are necessary for the efficient and effective design of wireless devices at any frequency, but will be especially important for 60 GHz devices intended for use with extremely wide-band signals. Previous generations of wireless technology relied on channel models that, for the most part, did not take into account frequency-dependent dispersion. This was possible because of the relatively narrow bandwidths of the signals used by previous technologies. For 60 GHz applications to be successful, they must be designed with more sophisticated channel models that account for frequency-dependent channel dispersion characteristics. Using sophisticated laboratory equipment allows Rappaport’s team to conduct measurement campaigns to improve knowledge of the 60 GHz channel.

Though they are actively researching improving 60 GHz channel models, their eventual goal is to combine what their knowledge of on-chip antennas and 60 GHz CMOS analog circuits to create a completely integrated, on-chip channel sounder. A channel sounder is a device that wireless researchers use to study the characteristics of a wireless channel. Currently, channel sounders, such as those in our lab, are bulky and difficult to transport, as they require several pieces of sub-equipment and separate antennas. Integrating all the elements of a channel sounder onto a single chip and measuring its performance against a current channel sounder’s capability will achieve two important goals: improving researchers’ ability to study the wireless channel and demonstrating the design and production of a highly-complex, fully-integrated 60GHz device.

Rappaport and his team have ambitious goals that require active collaboration with other researchers. They regularly collaborate with a wide range of researchers both at The University of Texas at Austin and across the country, including Prof. Talal Al-Attar of Santa Clara University. This research topic draws upon many disciplines within electrical engineering, and Rappaport hopes to continue to foster a spirit of collaboration both within the UT ECE department and with outside researchers.

For more information on our research:

F. Gutierrez, K. Parrish, T. S. Rappaport, “On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems,” IEEE Journal on Selected Areas in Communications, Vol. 27, Issue 8, October 2009, pp. 1367-1378.

T. S. Rappaport, F. Gutierrez, T. Al-Attar, “Millimeter-Wave and Terahertz Wireless RFIC and On-Chip Antenna Design: Tools and Layout Techniques,” invited conference paper, IEEE First Workshop on Millimeter Wave and Terahertz Communications, in conjunction with IEEE Global Communications Conference (Globecom), Honolulu, HI, November 30-December 4, 2009, pp. 1-7.