Professor Nur Touba was named an IEEE Fellow—the highest grade of IEEE membership—for contributions to test data compression and built-in self-test for integrated circuits. Dr. Touba has developed a number of innovative techniques for automated design of testable and fault-tolerant circuits.

In particular, his research has focused on developing new techniques for built-in self-test (BIST), test data compression, delay fault testing, concurrent error detection, and design-for-testibility (DFT) in core-based designs. His research helps reduce the cost and increase the quality of manufacturing tests.

Dr. Touba served as Program Chair for the 2008 International Test Conference, General Chair for the 2007 Symposium on Defect and Fault Tolerance, and Program Chair for 2008 International Test Synthesis Workshop.