Course Information
Instructor Details
- Instructor: Dr. Lizy Kurian John
- Office: ACES 3.114
- Office Hours: T,W,Th: 9:30-10:30am
- E-mail: ljohn@ece.utexas.edu
- Phone: (512)232-1455
- Homepage: http://www.ece.utexas.edu/~ljohn/
Course Details
- Time: T,Th 11-12:30pm
- Place: ENS 302
- Course Outline: outline.doc
Course Resources
- Textbook: C.H. Roth, Digital Systems Design using VHDL, 4th Printing or 5th Printing preferred. Errata List
- Reference: C.H. Roth, Fundamental of Logic Design, 5th Edition
- Computer Lab: We will use the computer labs in ENS308, ENS340, ENS317, and ENS507. Software packages for logic design, digital system simulation, gate array design, VHDL, etc. are available in the lab.
TA Details:
*note: Do not email the TAs with general lab questions, use the newsgroup!- TA 1: Jason Matalka
- TA 2: Kaushik Nadadhur
- TA Hours Schedule: labhours.xls
Notices
Mar 31 : Lab 6+7 duedates extended.
Mar 20 : Lab 6 & 7 posted. Get started early!
Mar 3 : Lab 5 posted.
Feb 23 : Lab 4 posted.
Feb 15 : Added sample test 1
Newsgroup Information
Please Note: Access to the class newsgroup is mandatory!
The EE360M Newsgroup is: utexas.class.ee360m
Help with Newsgroup Access:
- ECE Newsgroup Access Instructions
- UT Usenet Home Page - Free UT newsgroup access instructions
- Usenet FAQ - General information
- Mozilla Thunderbird - Free email/newsgroup reader
Newsgroup Policies
- As part of UT ICS policy, you must post with your REAL NAME.
- Please do not email the TAs with any general lab questions, use the newsgroup.
- Important class announcements will often be posted only to the newsgroup, so check it often.
Lab Resources
Lab Information -- Software Related
- XILINX Library Compents PDF
- XILINX ISE Tutorial
- XILINX ISE Webpack download and installation instructions
- ModelSim Tutorial
- Modelsim Shell Commands
- IEEE Libraries Overview
- VHDL Links
Lab Information -- Hardware Related
Lab Information -- Misc
Lab Guidelines
Lab Assignments
Lab Grading Policy
- 2 Days Early : +2%
- 1 Day Early : + 1%
- 1 Day Late : -10%
- 2 Days Late : -20%
Lab #1
- Lab 1 Description [Due Feb 2] (do not do problem 1.9)
Lab #2
- Lab 2 Description [Due Feb 9]
Lab #3
- Lab 3 Description [Due Feb 23]
- Counter Example 1
- Counter Example 2
Lab #4
- Lab 4 Description [Due Mar 9]
- See the Spartan-3 Users Manual for 7 Segment LED information.
Lab #5
- Lab 5 Description [Due Mar 23]
Lab #6
- Lab 6 Description[Due Apr 13]
- Lab 6 Cover Page
- Simple MIPS Example
- Block RAM Example
- Block RAm Example 2
- Distributed RAM Example
- Distrivuted ROM Example
Lab #7
- Lab 7 Description [Due Apr 25 & May 2] Tuesdays!
- Lab 7 Cover Page
Homework
Homework #1
- Problems: 1.2, 1.5, 1.10(a) and (b), 1.12, 1.15 [Due Jan 31]
Class Slides
Help with Newsgroup Access:
- ECE Newsgroup Access Instructions
- UT Usenet Home Page - Free UT newsgroup access instructions
- Usenet FAQ - General information
- Mozilla Thunderbird - Free email/newsgroup reader
Newsgroup Policies
- As part of UT ICS policy, you must post with your REAL NAME.
- Please do not email the TAs with any general lab questions, use the newsgroup.
- Important class announcements will often be posted only to the newsgroup, so check it often.
Lab Resources
Lab Information -- Software Related
- XILINX Library Compents PDF
- XILINX ISE Tutorial
- XILINX ISE Webpack download and installation instructions
- ModelSim Tutorial
- Modelsim Shell Commands
- IEEE Libraries Overview
- VHDL Links
Lab Information -- Hardware Related
Lab Information -- Misc
Lab Guidelines
Lab Assignments
Lab Grading Policy
- 2 Days Early : +2%
- 1 Day Early : + 1%
- 1 Day Late : -10%
- 2 Days Late : -20%
Lab #1
- Lab 1 Description [Due Feb 2] (do not do problem 1.9)
Lab #2
- Lab 2 Description [Due Feb 9]
Lab #3
- Lab 3 Description [Due Feb 23]
- Counter Example 1
- Counter Example 2
Lab #4
- Lab 4 Description [Due Mar 9]
- See the Spartan-3 Users Manual for 7 Segment LED information.
Lab #5
- Lab 5 Description [Due Mar 23]
Lab #6
- Lab 6 Description[Due Apr 13]
- Lab 6 Cover Page
- Simple MIPS Example
- Block RAM Example
- Block RAm Example 2
- Distributed RAM Example
- Distrivuted ROM Example
Lab #7
- Lab 7 Description [Due Apr 25 & May 2] Tuesdays!
- Lab 7 Cover Page
Homework
Homework #1
- Problems: 1.2, 1.5, 1.10(a) and (b), 1.12, 1.15 [Due Jan 31]
Class Slides
Handouts
Sample Tests
Test Solutions
Not available yet.