University of Texas
ECE

Is Hardware Innovation Over?

Part of Seminar Series: ECE Distinguished Lecture Series

Date: Monday, April 17, 2006
Time: 3:30 p.m.
Location: ACES Auditorium, ACES 2.302

Arvind

Arvind
Computer Science and Artificial Intelligence Laboratory, MIT

Abstract

Does the spread of multicore architectures mean the demise of Application Specific Integrated Circuits (ASIC)? Power constrained, handheld devices may be one of the most important economic drivers for the semiconductor industry in the coming decades. Will the future cell phone functionality be delivered primarily through multi-core processors? Or will it be through reconfigurable FPGAs or a system composed of heterogeneous blocks? We will describe how it is possible to synthesize, quickly and efficiently, large and complex SoC’s from a library of microarchitectural IP blocks, including embedded PowerPC models, DSPs and a variety of specialized hardware blocks (radios, MPEG4 decoders, ...). Our project, will provide, among other things, PowerPC “gateware” for others to use, and will shed light on how IP blocks should be written to be easily modifiable and reusable.

Speaker Biography

Arvind is the Johnson Professor of Computer Science and Engineering at MIT where he has been since 1979. In 1992, his group, in collaboration with Motorola, built the Monsoon dataflow machines and its associated software. A dozen of these machines were built and installed at Los Alamos National Labs and other universities, before Monsoon was retired to the Computer Museum in California.

In 2000, Arvind took a two-year leave of absence to start Sandburst, a fabless semiconductor company to produce a chip set for 10G-bit Ethernet routers. In 2003, Arvind co-founded Bluespec Inc., an EDA company to produce a set of tools for high-level synthesis. He currently serves on the board of both Sandburst and Bluespec.

In 2001, Dr. R. S. Nikhil and Arvind published the book "Implicit parallel programming in pH". Arvind's current research interests are synthesis and verification of large digital systems described using Guarded Atomic Actions; and Memory Models and Cache Coherence Protocols for parallel architectures and languages.