Scaling the Memory Wall with Phase Change Memories

Abstract

DRAM has been the building block for main memory systems for several decades. However, with each technology generation, significant portion of the total system power and the total system cost is spent in the DRAM memory system, and this trend continues to grow making DRAM a less desirable choice for future larger system memories. Therefore, architects and system designers must look at alternative technologies for growing memory capacity. Phase-Change Memory (PCM) is an emerging technology which is denser than DRAM and can boost memory capacity in a scalable and power-efficient manner. However, PCM has its own unique challenges such as higher read latency (than DRAM), much higher write latency, and limited lifetime due to write endurance.

In this talk I will focus on architectural solutions that can leverage the density and power-efficiency advantages of PCM while addressing its challenges. I will propose a “Hybrid Memory” system that combines PCM-based main memory with a DRAM buffer, thereby obtaining the capacity benefits of PCM and latency benefits of DRAM. I will then describe a simple, novel, and efficient wear leveling technique for PCM memories that obtains near-perfect lifetime while incurring a storage overhead of less than 13 bytes. Finally, I will provide extensions to PCM memories than can adaptively “cancel” or “pause” write requests to reduce latency of read requests when there is significant contention from the (slow) write requests.

Speaker Biography

Dr. Moinuddin Qureshi is a research staff member at IBM Research. His research interest includes computer architecture, scalable memory system, fault tolerant systems, and analytical modeling of computer systems. His recent research effort is focused on exploiting emerging technologies for scalable and power-efficient memories and has led to the following contributions: Hybrid memory system using PCM (ISCA’09), efficient wear leveling for PCM (MICRO’09), and write pausing in PCM (HPCA’10). He holds three US patents and has more than a dozen publications in flagship architecture conferences. He contributed to the development efficient caching algorithms for Power 7 processors. He received his PhD from the University of Texas at Austin in 2007.