Seminars

Decoupled Look-ahead Architectures

Tuesday, March 20, 2012

Dr. Michael Huang

Abstract

Conventional look-ahead architecture has been a powerful driver to deliver the single-thread performance that we see today. However, with frequency scaling plateaued, single-thread performance improvement has significantly slowed. With the prevalence of multicore architecture in the marketplace and the increasing core count, some believe single-thread performance is no longer relevant and that everybody *has* to start parallel programming. If only that is the solution! It is probably safe to say that we are entering an era where cheap, effective performance tricks are becoming rare and we have to increasingly diversify the source of performance improvement. Nevertheless, there is no evidence that implicit parallelism has been exhausted. We believe that with more effort, we can still find significant performance enhancement opportunities. And exploiting implicit parallelism through look-ahead is still a valid principle. Conventional look-ahead implementation is the product of a lengthy evolution and is not the only way of carrying out look-ahead. We have been experimenting a more decoupled design of the look-ahead logic. From what we learned, it appears to us that practical implementations that offer tangible performance benefits at reasonable energy costs are achievable. In this talk, I will discuss some specific ideas and point to some future directions that we are currently exploring.

Speaker Biography

Michael Huang received the BS degree in computer science and engineering from Tsinghua University, Beijing, in 1994, the MS and the PhD degree in computer science from University of Illinois at Urbana-Champaign in 1999 and 2002, respectively. From 1994 to 1997, he was a lead architect in building a 32-processor hierarchical shared-memory multiprocessor research prototype. He joined the faculty of the Electrical and Computer Engineering department in 2002, where he is now an Associate Professor. In 2010, he was on sabbatical at IBM T. J. Watson Research Center working on future POWER processor concept development.

His research interests include various aspects of high-performance computer architecture such as processor microarchitecture, communication and memory substrate, reliability, and energy-efficient and complexity-effective design. He is particularly interested in addressing emerging issues and exploring new capabilities in the underlying device, circuit, and manufacturing technology. He is a recipient of the NSF CAREER award and a member of the IEEE and the ACM.