| PD |
I. Liu, H. Chen, A. Aziz, and D.F. Wong.
``Integrated Power Supply Planning and Floorplanning.''
ASP Design Autmation Conference. January 2001.
| Verif-Prac |
J. Yuan, K. Schultz, C. Pixley, H. Miller, and A. Aziz, Automatic Vector
Generation Using Constraints and Biasing, Journal of Electronic Testing:
Theory and Applications (2000), 107--120.
|
| Seq-Syn |
A. Aziz, F. Balarin, R. Brayton, and A. Sangiovanni-Vincentelli,
Sequential Synthesis Using S1S, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 19 (2000),
no. 10.
|
| PD |
H. Zhou, D. F. Wong, I. Liu, and A. Aziz, Simultaneous Routing and
Buffer Insertion with Restrictions on Buffer Locations, IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems 19
(2000), no. 7, 819--824.
|
| Verif-Prac |
Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming
Andersen: An Abstraction Algorithm for the Verification of Generalized
C-Slow Designs. CAV 2000: 5-19
|
| Verif-Thy |
A. Aziz, K. Sanwal, V. Singhal, and R. Brayton, Model-Checking
Continuous Time Markov Chains, ACM Transactions on Computational Logic
1 (2000), no. 1, 162--170.
|
| Verif-Prac |
Praveen Yalagandula, Vigyan Singhal, and Adnan Aziz.
Automatic Lighthouse Generation for Directed State Space Search. In Proc.
of Design Automation and Test in Europe, Paris, FRANCE,
March 2000. |
| PD |
I-Min Liu, Adnan Aziz, and Martin Wong.
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. In Proc.
of Design Automation and Test in Europe, Paris, FRANCE,
March 2000. |
| Verif-Prac |
Jun Yuan, Kurt Schultz, Carl Pixley, Hiller Miller, and Adnan Aziz.
Modeling
Design Constraints and Biasing Using BDDs in Simulation In Proc.
of International Conference on Computer-Aided Design, Santa Clara,
CA, Nov 1999. |
| PD |
I-Min Liu, Adnan Aziz, and Martin Wong. An
Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian
Relaxation. Intl. Conf. on Computer Design, Austin, TX, October
1999. |
| Verif-Prac |
Jason Baumgartner, Tamir Heyman, Vigyan Singhal, and Adnan Aziz.
Model
Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High
Performance Netlists. In Proc. of Computer-Aided Verification Conference,
Trento, ITALY, July 1999. |
| PD |
Hai Zhou, Martin Wong, I-Min Liu, and Adnan Aziz. Simultaneous
Routing and Buffer Insertion with Restrictions on Buffer Locations. In
Design
Automation Conference, New Orleans, LA, June 1999. |
| Verif-Prac |
Malay Ganai, Adnan Aziz, and Andreas Kuehlmann.
Augmenting
Simulation with Symbolic Algorithms In Proc. of Design Automation
Conference, New Orleans, LA, June 1999. |
| Verif-Prac |
Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini,
Adnan Aziz, and Lizy K. John.
Formal Verification
of a Snoop Based Cache Coherency Protocol. In Proc. of VLSI Design
Conference, Goa, INDIA, Jan 1999. |
| Comb-Syn |
Tai-Hung Liu, Malay Ganai, Adnan Aziz, and Jeff Burns. Performance
Driven Synthesis for Pass-Transistor Logic Circuits. In VLSI Design
Conference, Goa, INDIA, Jan 1999. |
| Verif-Prac |
James Kukula, Tom Shiple, and Adnan Aziz.
Techniques
for implicit state enumeration of EFSMs. In Proc. of Formal Methods
in Computer-Aided Design, Palo Alto, CA, Nov 1998. |
| Comb-Syn |
Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, and Jeff Burns. Area
Oriented Synthesis for Pass-Transistor Logic. Intl. Conf. on Computer
Design, Austin, TX, October 1998. |
| Verif-Thy |
Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, and Vigyan Singhal.
Symbolic
Procedures for a Theory of Equality with Uninterpreted Functions. In
Proc.
of Conference on Computer-Aided Verification, Vancouver, CANADA, July
1998. |
| Verif-Prac |
Yufeng Luo, Tjahjadi Wongsonegoro, and Adnan Aziz. Hybrid
Techniques for Fast Functional Simulation. In Proc. of Design Automation
Conference, San Francisco, CA, June 1998. |
| Verif-Prac |
Adnan Aziz, Thomas R. Shiple, and James H. Kukula. Hybrid
Verification Using Saturated Simulation. In Proc. of Design Automation
Conference, San Francisco, CA, June 1998. |
| Verif-Prac |
Malay Ganai and Adnan Aziz. Efficient Coverage
Directed State Space Search. In Proc. of International Workshop
on Logic Synthesis, Lake Tahoe, CA, June 1998. |
| Seq-Syn |
Hai Zhou, Vigyan Singhal, and Adnan Aziz. How
powerful is retiming? In Proc. of International Workshop on Logic
Synthesis, Lake Tahoe, CA, June 1998. |
| PD |
Tai-Hung Liu, Hai Zhou, and Adnan Aziz. Simultaneous
PTL Buffer Insertion and Sizing for Minimizing Elmore Delay. In Workshop
Notes of Intl. Workshop on Logic Synthesis, Tahoe City, CA, May 1998. |
| PD |
Hai Zhou and Adnan Aziz. Buffer
Minimization in Pass Transistor Logic. In Workshop Notes of
Intl. Workshop on Logic Synthesis, Tahoe City, CA, May 1998. |
| Seq-Syn |
Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Adnan Aziz, Robert K. Brayton,
and Alberto Sangiovanni-Vincentelli.
Sequential
Redundancy Identification and Removal Without Search. Intl. Conf.
on Computer-Aided Design, San Jose, CA, November 1997. |
| Verif-Prac |
Jun Yuan, Jian Shen, Jacob Abraham, and Adnan Aziz.
On
Combining Formal and Informal Verification. In Proc. of Conference
on Computer-Aided Verification, Haifa, ISRAEL, July 1997. |
| Comb-Syn |
Tai-Hung Liu, Khurram Sajid, Adnan Aziz, and Vigyan Singhal.
Optimizing
Designs Containing Black Boxes. In Proc. of Design Automation Conference,
Anaheim, CA, June 1997. |
| Verif-Prac |
William N. N. Hung, Adnan Aziz, and Ken McMillan.
Heuristic
Symmetry Reduction for Invariant Checking. In Workshop Notes of
Intl. Workshop on Logic Synthesis, Tahoe City, CA, May 1997 |
| Verif-Prac |
R.K. Brayton, A. Sangiovanni-Vincentelli, G.D. Hachtel, F. Somenzi,
A. Aziz, S.-T. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, S. Qadeer, R.K.
Ranjan, T.R. Shiple, G. Swamy, T. Villa, A. Pardo, and S. Sarwary. VIS.
In Proc. of Conference on Formal Methods in Computer-Aided Design,
Santa Clara, CA, Nov 1996. |
| Verif-Thy |
Adnan Aziz, Kumud Sanwal, Vigyan Singhal, and Robert K. Brayton.
Verifying
Continuous Time Markov Chains. In Proc. of Conference on Computer-Aided
Verification, Rutgers, NJ, July 1996. |
| Verif-Prac |
R.K. Brayton, A. Sangiovanni-Vincentelli, G.D. Hachtel, F. Somenzi,
A. Aziz, S.-T. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, S. Qadeer, R.K.
Ranjan, T.R. Shiple, G. Swamy, T. Villa, A. Pardo, and S. Sarwary. VIS:
A system for verification and synthesis. In Proc. of Conference
on Computer-Aided Verification, Rutgers, NJ, July 1996. |
| Misc. |
Adnan Aziz
Formal
Methods in VLSI System Design. PhD Thesis. UC Berkeley 1996. |
| Verif-Thy |
Adnan Aziz, Robert K. Brayton, Felice Balarin and Vigyan Singhal.
Timing-Safe
Replaceability for Combinational Logic. TAU 1995, Seattle, WA,
November 1995. |
| Seq-Syn |
Adnan Aziz, Felice Balarin, Robert K. Brayton and Alberto Sangiovanni-Vincentelli.
Sequential
Synthesis Using S1S. In Proc. of Intl. Conf. on Computer-Aided Design,
San Jose, CA, November 1995. |
| Seq-Syn |
Vigyan Singhal, Carl Pixley, Adnan Aziz and Robert K. Brayton.
Exploiting
Power-up Delay for Sequential Optimization. In Proc. of European
Design Automation Conference, Brighton, Great Britain, September 1995. |
| Verif-Thy |
Adnan Aziz, Felice Balarin, Marika DiBenedetto, Robert K. Brayton,
Alex Saldanha and Alberto Sangiovanni-Vincentelli.
Supervisory
Control of Finite State Machines. In Proc. of Conference on Computer-Aided
Verification, Liege, Belgium, July 1995. |
| Verif-Thy |
Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton and Alberto
L. Sangiovanni-Vincentelli.
It
Usually Works: The Temporal Logic of Stochastic Systems. In Proc.
of Conference on Computer-Aided Verification, Liege, Belgium, July
1995. |
| Verif-Prac |
Rajeev K. Ranjan, Adnan Aziz, Robert K. Brayton, Carl Pixley and Bernhard
Plessier.
Efficient
BDD Algorithms for Synthesizing and Verifying Finite State Machines.
In Workshop Notes of Intl. Workshop on Logic Synthesis, Tahoe City,
CA, May 1995. |
| Seq-Syn |
Carl Pixley, Vigyan Singhal, Adnan Aziz and Robert K. Brayton.
Multi-level
Synthesis for Safe Replaceability. In Proc. of Intl. Conf. on Computer-Aided
Design, San Jose, CA, November 1994. |
| Verif-Prac |
Adnan Aziz, Vigyan Singhal, Gitanjali M. Swamy and Robert K. Brayton.
Minimizing
Interacting Finite State Machines: A Compositional Approach to Language
Containment. In Proc. of Intl. Conf. on Computer Design, Cambridge,
MA, October 1994. |
| Verif-Thy |
Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton and Alberto
L. Sangiovanni-Vincentelli.
Equivalences
for Fair Kripke Structures. In Proc. of Intl. Colloquim on Automata,
Languages and Programming, Jerusalem, Israel, July 1994. |
| Verif-Thy |
Adnan Aziz, Thomas R. Shiple, Vigyan Singhal and Alberto L. Sangiovanni-Vincentelli.
Formula-Dependent
Equivalence for CTL Model Checking. In Proc. of Conference on Computer-Aided
Verification, Stanford, CA, June 1994. |
| Verif-Prac |
Adnan Aziz, Serdar Tasiran and Robert K. Brayton.
BDD
Variable Ordering for Interacting Finite State Machines. In Proc.
of Design Automation Conference, San Diego, CA, June 1994. |
| Verif-Prac |
A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S.C. Krishnan,
R.K. Ranjan, T.R. Shiple, V. Singhal, S. Tasiran, H.-Y. Wang, R.K. Brayton
and A.L. Sangiovanni-Vincentelli.
HSIS:
A BDD-based Environment for Formal Verification. In Proc. of Design
Automation Conference, San Diego, CA, June 1994. |
| Verif-Prac |
T. Shiple, A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S.
Krishnan, V. Singhal, H.-Y. Wang, R. Brayton and A. Sangiovanni-Vincentelli.
Formal
Design Verification of Digital Systems. In Proc. SRC TECHCON,
Atlanta, GA, September 1993. |
| Verif-Thy |
Adnan Aziz, Vigyan Singhal and Robert K. Brayton. Verifying
Interacting Finite State Machines: Complexity Issues. Memorandum No.
UCB/ERL M93/52, Electronics Res. Lab., Cory Hall, University of California,
Berkeley, CA 94720. |
|