me

Moinuddin K. Qureshi

I have graduated and am now a research scientist at the IBM T.J.Watson Research Center.

I was a graduate student at the ECE department of UT Austin.  I am a part of the HPS research group.  My research is directed towards enhancing the performance and dependability of computer systems. I am interested in high performance cache design,  utility-aware memory system design, and fault-tolerant microarchitecture.

I can be reached at  my:
Phone:  512-565-9463
Email:   moin AT hps.utexas.edu
Office:  ENS 532, The University of Texas, Austin. TX 78712-1084
Publications
  • An Asymmetric Multi-core Architecture for Accelerating Critical Sections.
    M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi and Yale N. Patt
    To appear in the International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS) 2009.

  • Dynamic Spill-Accept for Scalable High-Performance Caching in CMPs.
    Moinuddin K. Qureshi
    To appear in the International Conference on High Performance Computer Architecture (HPCA) 2009.

  • Adaptive Insertion Policies for Managing Shared Caches. (pdf, slides, code)
    Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon Stelly Jr. and Joel Emer
    Appears in the International Conference on Parallel Architectures and Compiler Techniques (PACT) 2008.

  • Feedback Driven Threading: Power-Efficient and High-Performance Execution of Multithreaded Workloads on CMPs. (pdf)
    M. Aater Suleman, Moinuddin K. Qureshi, and Yale N. Patt.
    Appears in the International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS) 2008.

  • Set-Dueling Controlled Adapative Insertion for High-Performance Caching.
    Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt,  Simon C. Steely Jr., and Joel Emer.
    Appears in the IEEE MICRO Special Issue on Top Picks from Microarchitecture Conferences (IEEE MICRO 2008).

  • Adaptive Insertion Policies for High-Performance Caching. (pdf, slides, code)
    Moinuddin K.Qureshi, Aamer Jaleel, Yale N. Patt,  Simon C. Steely Jr., and Joel Emer.
    Appears in the International Symposium on Computer Architecture (ISCA) 2007.

  • Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. (pdf, slides)
    Moinuddin K. Qureshi, M. Aater Suleman, and Yale N. Patt.
    Appears in the International Symposium on High-Performance Computer Architecture (HPCA) 2007.

  • Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. (pdf, slides)
    Moinuddin K. Qureshi and Yale N. Patt.
    Appears in the International Symposium on Microarchitecture     (MICRO) 2006.

  • A Case for MLP-Aware Cache Replacement.  (pdf, slides, code)
    Moinuddin K. Qureshi,  Daniel Lynch, Onur Mutlu, and Yale N. Patt.
    Appears in the International Symposium on Computer Architecture (ISCA) 2006.

  • The V-Way Cache: Demand Based Associativity via Global Replacement. (pdf, slides, code)
    Moinuddin K. Qureshi,  David Thompson, and Yale N. Patt.
    Appears in the International Symposium on Computer Architecture (ISCA) 2005.

  • Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in  Microprocessors. (pdf, slides)
    Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt.
    Appears in the IEEE International Conference on Dependable Systems and Networks     (DSN) 2005.
    •  
    A full listing of patent applications and invention disclosures is available here. 
Me, Myself, and Moin
  • Hiking :    List of hikes that I have been to
  • Books  :    Few and far between
  • Quotes :    Some good ones
" In a good cause there are no failures, there are only delayed successes" - Asimov