Nur A. Touba - Biography

Nur Touba was born and raised in suburban Minneapolis. He did his undergraduate work at the University of Minnesota where he graduated Summa Cum Laude. He received a graduate fellowship at Stanford University. At Stanford, he worked with Prof. Edward McCluskey at the Center for Reliable Computing. He completed his Ph.D. in 1996. He received a National Science Foundation (NSF) Early Faculty CAREER Award in 1997, College of Engineering Foundation Faculty Award in 2001, Best Paper Award at the VLSI Test Symposium in 2001, Best Panel Award at the International Test Conference in 2005, and General Motors Faculty Fellowship in 2006.

Dr. Touba's research interests are in VLSI testing and fault-tolerant computing. He has developed a number of innovative techniques for automated design of testable and fault-tolerant circuits. In particular, his research has focused on developing new techniques for test data compression, built-in self-test (BIST), delay fault testing, concurrent error detection, and design-for-testability (DFT) in core-based designs.

Dr. Touba is currently serving as Program Chair for the 2008 International Test Conference, General Chair for the 2007 Symposium on Defect and Fault Tolerance, and Program Chair for 2008 International Test Synthesis Workshop. He is on the program committee for the International Test Conference (ITC), International Conference on Computer Design (ICCD), Design Automation and Test in Europe Conference (DATE), International On-Line Test Symposium (IOLTS), European Test Symposium (ETS), Asian Test Symposium (ATS), Defect and Fault Tolerance Symposium (DFTS), International Test Synthesis Workshop (ITSW), Latin American Test Workshop (LATW), Microprocessor Test and Verification Workshop (MTV), International Workshop on Open Source Test Technology Tools (IOST3), and ATE Vision 2020 Workshop. He is on the editorial board of the Journal of Low Power Electronics (JOLPE).

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