ANATOMY: An Analytical Model of Memory System Performance

Seminar
Sunday, February 02, 2014
6:00 PM
POB 2.402
Free and open to the public

Memory system design is increasingly influencing modern multi- core architectures from both performance and power perspectives. However the problem of designing efficient memory systems is compounded by the myriad design choices and parameters along multiple dimensions. In this work, we construct an analytical model of the memory system to comprehend this diverse space and to study the impact of memory system parameters from latency and bandwidth perspectives. Our model, called ANATOMY, consists of two key components that are coupled with each other, to model the memory system accurately. The first component is a queuing model of memory which models in detail various design choices and captures the impact of technological choices in memory systems. The second component is an analytical model to summarize key workload characteristics, namely row buffer hit rate (RBH), bank-level parallelism (BLP), and request spread (S) which are used as inputs to the queuing model to estimate memory performance. We demonstrate the extensibility and applicability of our model by exploring a variety of memory design choices such as the impact of clock speed, benefit of multiple memory controllers, memory scheduling, the role of banks and channel width, and memory refresh.

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Speaker

Govindarajan Ramaswamy

Chairman
Supercomputer Education and Research Centre

Govindarajan Ramaswamy received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of Science, Bangalore in 1984 and 1989 respectively. He has held postdoctoral research positions and visiting faculty positions at Universities in USA and Canada. Since 1995, he has been with the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore. Currently he is a professor and the chairman of the Supercomputer Education and Research Centre. His research interests are in the areas of High Performance Computing, Compilation Techniques, and Computer Architecture.