Circuit Techniques for Combating CMOS Reliability and Variability Effects

Monday, October 17, 2011
7:00 PM
Free and open to the public

In order to continue CMOS scaling towards the physical limit, care must be taken to account for each obstacle that is currently impeding our progress. The impact of Process-Voltage-Temperature (PVT) variations on circuit performance has increased with device scaling. Reliability issues such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI) and dielectric breakdown have become serious problems degrading the long term yield of high performance systems. Increased power consumption and faster current transients have deteriorated on-chip power supply integrity. The need for a robust high-density on-chip memory will continue to grow in future multicore processors. In this talk, I will introduce some of the on-going research activities in the VLSI design group at the University of Minnesota concerning low voltage digital, mixed-signal, and memory circuit design in the nanometer regime. Topics will range from on-chip reliability monitors and supply noise mitigation techniques to practical demonstrations of low voltage SRAM and DRAM as well as future prospects on spin-torque-transfer RAM.

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Chris H. Kim

Associate Professor
University of Minnesota