Clock and Data Recovery Techniques for Optical Communication Systems

Seminar
Monday, October 24, 2016
1:00 PM to 3:00 PM
POB 2.402
Free and open to the public

Clock and Data Recovery (CDR) is a key function in a communication system. We begin this part of the course with a review of the fundamentals of CDR in Non-Return-to-Zero (NRZ) serial links. System level metrics like jitter-tolerance, jitter-transfer and jitter-generation are introduced to evaluate the performance of a CDR. Several CDR architectures are discussed. Their advantages and drawbacks specifically for high-speed optical systems are compared. Many optical systems require a reference-less CDR. Various techniques to extract frequency from the incoming data are explained in detail. Linear and bang-bang phase detectors at full-rate are introduced. Sub-rate structures that ease the speed requirements of the circuits are also described.

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Speaker

Kadaba R. (Kumar) Lakshmikumar

Cisco Systems

Kadaba R. (Kumar) Lakshmikumar received his B.E. and M.E. degrees in Electrical Communication Engineering from the Indian Institute of Science, Bangalore, India, and Ph.D. degree in Electrical Engineering from Carleton University, Ottawa, Canada. He did pioneering work in the area of modeling mismatch in MOS devices for his doctoral work. The standard deviation of mismatch was shown to be inversely proportional to the square-root of the channel area. His paper in the December 1986 issue of the IEEE Journal of Solid-State Circuits is among the top 20 cited publications of the journal between 1968 and 1992. (http://www.ieee.org/organizations/pubs/newsletters/sscs/oct02/TopArticles.html.) Lakshmikumar has made lasting contributions to the field of IC design through his leadership in identifying and solving technically challenging problems. He presented a tutorial titled “PLL Design in Nanometer CMOS” at ISSCC 2010. The tutorial (http://sscs.ieee.org/tutorials-online/2010-issccshort-courses-and-tutorials/426-isscc-2010-tutorial-pll-design-in-nanometercm...) illustrates design techniques for overcoming large variability, low supply voltage and high leakage. In 2015, he presented a short course, “Clock and Data Recovery Techniques for Optical Communication Systems” at CSICS. Many reference-less CDR architectures are discussed here. He has held senior engineering positions at Bell Labs, Multilink and Conexant Systems. Currently he is heading the analog design group at Cisco Systems’ Silicon Photonics division in Allentown, PA. He has served on the Technical Program Committees of IEEE Custom Integrated Circuits Conference and IEEE International Solid State Circuits Conference and Compound Semiconductor Integrated Circuits Symposium. He is an associate editor of the IEEE Journal of Solid-State Circuits. He has mentored a number of graduate students and serves as an external examiner for Ph.D. candidates. Lakshmikumar is a Fellow of IEEE.