A Convergent Architecture for Big Data, Machine Learning and Real-Time Computing

Tuesday, February 28, 2017
9:30 AM
POB 2.302 (Avaya)
Free and open to the public

In the quest for more intelligent consumer devices, machine learning lets appliances understand what is happening around the computer and what is asked of it, while big data provides the history and context of the environment.  But devices must also react to be useful, and for many applications the reaction needs to happen on human timescale to be valuable.  For example, an advertisement beacon must beam a discount coupon to the shopper's cellphone in a few hundred milliseconds or the shopper will walk past.  Today many people prefer to use large shared data centers remotely accessed through the public internet for big data analytics and machine learning because this is the most cost-effective and energy efficient way to do large-scale computing.  But integrating real-time computing with big data and machine learning may make that impractical because exchanging messages through the internet may itself consume a substantial fraction of a second, leaving almost no time for computing if you want to guarantee application response time of a few hundred milliseconds.  In this talk I propose a FLASH-based parallel computer using large numbers of low-power processor chips with vector units.  Such a system is very much smaller, cheaper and lower power than one with equal memory capacity and instruction throughput made entirely with DRAM, x86 processors and GPUs.  It is small enough to install locally in retail and office locations or mobile platforms such as trucks and ships, and inexpensive enough that it need not be a shared computing resource.  Yet because it uses primarily FLASH memory, which is extremely dense, the storage capacity can be as big or bigger than any DRAM-based in-memory big data analytic server.

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Peter Hsu

Peter Hsu was born in Hong Kong and moved to the United States as a teenager.  He received a B.S. degree from the University of Minnesota at Minneapolis in 1979, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign in 1983 and 1985, respectively, all in Computer Science.  His first job was at IBM T. J. Watson Research Center from 1985-1987, working on code generation techniques for superscalar and out-of-order processors with the 801 compiler team.  He then joined one of his former professor at Cydrome, which developed an innovative VLIW computer.  In 1988 he moved to Sun Microsystems and tried to build a water-cooled gallium arsenide SPARC processor, but the technology was not sufficiently mature and the effort failed.  He joined Silicon Graphics in 1990 and designed the MIPS R8000 TFP microprocessor.   The R8000 was released in 1994 and shipped in the SGI Power Challenge servers and Power Indigo workstations.  Fifty of the TOP500.org list of supercomputer systems used R8000 chips in 1994.  Peter became a Director of Engineering at SGI, then left in 1997 to co-found his own startup, ArtX, best known for designing the Nintendo GameCube.  ArtX was acquired by ATI Technologies in 2000.  He left ArtX in 1999 and worked briefly at Toshiba America, where he developed advanced place-and-route methodologies for high frequency microprocessor cores in SoC designs, then became a visiting Industrial Researcher at the University of Wisconsin at Madison in 2001.  Throughout the 2000’s he consulted for various startups, attended the Art Academy University and the California College of the Arts in San Francisco where he learned to paint oil portraits, attended a Paul Mitchell school where he learned to cut and color hair.  In the late 2000’s he consulted for Sun Labs, which lead to discussions about the RAPID research project, a power-efficient massively parallel computer for accelerating big data analytics in the Oracle database.  Peter joined Oracle Labs as an Architect in 2011.  He became an independent researcher in early 2016.