Designing Extremely Efficient Computers

Tuesday, March 10, 2015
3:30 PM to 4:30 PM
GDC 6.302
Free and open to the public

For decades technology scaling has decreased the cost of computing to the point where it can be included in almost anything. We have become accustomed to computing becoming faster, cheaper, and lower power, so we simply assume it will continue. While scaling has never been easy, a number of factors have made scaling increasingly difficult this past decade, and have caused power to become the principal constraint on performance. To continue scaling, new technologies (e.g., memristors, carbon nanotubes, resistive memories, magnetic memories) are considered these days as replacements to CMOS technology. 

In this talk, I show that the way to achieve high energy efficiency is by designing hardware that is tightly matched with the application. This hardware can exploit novel characteristics of new technologies to complement CMOS technology, rather than completely replace CMOS. 

I show how image processing algorithms that are used in many mobile devices share similar behavior that can be exploited to increase hardware efficiency, and how memory technologies can also perform logic operations, enabling non-von Neumann computers and tight integration with CMOS technology. 

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Shahar Kvatinsky

Stanford University

Shahar Kvatinsky received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009 he was with Intel as a circuit designer. He is currently a post-doctoral research fellow at Stanford University. His current research is focused on circuits and architectures with emerging memory technologies and design of energy efficient architectures.