Current projections suggest semiconductor scaling will end around the 7nm process node in less than 10 years. Hence, obtaining continued reductions in the cost of computation will soon require more efficient architectures. One way to improve architecture efficiency is using accelerators. However, current accelerator architectures such as graphics processor units (GPUs) introduce numerous challenges for programmers. Consequently they are often seen as suitable only for a narrow range of applications such as high performance computing. This talk will describe recent research on architecture changes such as introducing transactional memory and coherence into GPUs to broaden the range of applications that benefit from accelerators.
Tuesday, April 23, 2013
Free and open to the public