Energy-efficient Circuits for Entropy Generation & Side-Channel-Resistant Encryption

Tuesday, March 03, 2020
11:15 AM to 12:15 PM
EER 3.646
Free and open to the public

Physically Unclonable Functions (PUF) and True Random Number Generators (TRNG) are foundational security primitives underpinning the root of trust in computing platforms. Contradictory design strategies to harvest static and dynamic entropies typically necessitate independent PUF and TRNG circuits, adding to design cost. This tutorial describes a unified static and dynamic entropy generator leveraging a common entropy source for simultaneous PUF and TRNG operation. We will present self-calibration techniques to run-time segregate bitcells into PUF and TRNG candidates, along with entropy extraction techniques to maximize TRNG entropy while stabilizing PUF bits. Cryptographic circuits such as Advanced Encryption Standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCA), where an adversary monitors supply current signatures of a chip to decipher the value of embedded keys. This tutorial will also discuss the use of arithmetic/circuit countermeasures to minimize the correlation of the AES current to embedded keys, thereby improving the SCA resistance of the hardware by 1200x in both time and frequency-domains.


Sanu Mathew

Sanu Mathew

Intel Corporation

Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he heads the security arithmetic circuits research group, responsible for developing special-purpose hardware accelerators for cryptography and security. He received his Ph.D. degree in Electrical and Computer Engineering from State University of New York at Buffalo in 1999. He holds 62 issued patents, has 20 patents pending and has published over 80 conference/journal papers. He is a Fellow of the IEEE.