Scalability Challenges for Future Chip Multiprocessor Architectures

Wednesday, February 16, 2011
6:00 PM
Free and open to the public

Technology forecasts predict a biennial doubling of the number of processor cores for the next ten years. But the road forward to unleash their computational power to applications will be increasingly challenging. Some of these challenges are: i) how can architects provide a more productive interface to the software? ii) How can the memory system be architected so that memory bandwidth can scale up exponentially? iii) How can the chip resources be used to make the whole chip infrastructure scalable to a large number of processor cores. As for high-productivity hardware/software interfaces, I will talk about our recent contributions to realize hardware transactional memory and the direction we are taking beyond that towards a high-productivity hardware/software interface. Concerning memory systems there is considerable room for improvement in the utilization of on-chip memory resources. I will present work-in-progress on our value-centric approach in designing memory systems. Eventually, the serial bottleneck, so cleverly framed by Amdahl decades back, will hit us. If there is time, I will also talk about a design-space exploration exercise we did in which we have found that in some data mining applications that potentially scale to hundreds of cores, reduction operations can limit scalability substantially. Through validated analytical models, we find that while asymmetric chip multiprocessors intuitively could mitigate these serial bottlenecks, symmetric chip multiprocessors with more powerful cores appear to be a better pursuit.

Sponsored jointly by the Departments of Computer Science and Electrical and Computer Engineering and supported by a grant from IBM. Hosted by Prof. Yale Patt.

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Per Stenstrom

Chalmers University of Technology