What Could Possibly go Wrong? A Look at the Dark Side of Computer Architecture

Seminar
Computer Architecture
Tuesday, February 24, 2015
3:30 PM to 5:00 PM
POB 2.302
Free and open to the public

A clear market need, compelling usage models and a dream team create the perfect storm for a fantastically successful product.  Compromises, unforeseen challenges and poor decision making can conspire to turn a brilliant product into a merely successful endeavor.

This talk will explore the seedy underbelly of computer architecture and product definition.  It will look at things that went wrong and lessons learned from the execution of a major product development.  While the scope of the project was to create new business opportunities in excess of $1B, some of the lessons are surprisingly applicable to everyday computer architecture projects.

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Speaker

Doug Carmean

Microsoft

Doug is currently an Architect at Microsoft exploring the role of classical computer architectures in the context of complete quantum systems. Previously, Doug was an Intel Fellow and Director of the Efficient Computing Lab at Intel.

He is responsible for creating the vision and concept for the Xeon Phi family products, an architecture for highly parallel workloads including a high performance scientific applications based on Intel Architecture processors. Carmean led the team that founded a new group at Intel to define, build and productize the Xeon Phi family.

Doug joined Intel in 1989, he has held several key roles and provided leadership in Intel's microprocessor architecture development and product roadmap. As Nehalem's first chief architect, a next-generation x86 flagship processor, he led the team during the early phases of architecture definition. Prior to this position, he was a principal architect for the Pentium 4 processor where he completed the memory cluster and power architecture definition including algorithms, structures and overall functionality.

Carmean holds more than 25 patents and many pending in processor architecture and implementation, memory subsystems and low power design. He has published more than a dozen technical papers