Decades of research on branch prediction results in complex prediction algorithms and large look up tables,  leading to a multi-cycle prediction latency, adversely impacting performance. Ahead prediction is a proposed solution to the predictor latency problem, but drastically increases prediction energy as exponentially more entries are read out for each branch skipped, making building such a predictor impractical. In this talk, I will show that only a few missing history patterns are observed in the program's runtime. Using this insight, we present a new approach for building ahead predictors that does not require reading exponentially more entries for large ahead distances. Our ahead predictor provides a 4.4\% performance improvement while increasing power by only 1.5x, as opposed to prior designs that incur a 14.6x energy overhead. By hiding the predictor latency from the rest of the pipeline, our work allows for larger and more complex predictors and better pipelining width scaling. In addition, our work implies that the direction of an easy-to-predict branch does not need to be pushed to the history, presenting opportunities for future branch predictor design.

Bio: Chester is a 7th year PhD student studying CPU microarchitecture under Professor Yale Patt. His research focuses on the CPU frontend, specifically branch prediction, balancing predictor accuracy, latency and throughput. Before Joining UT Austin, he obained his bachelor degree in Computer Engineering from Rose-Hulman Institute of Technology.