As computation-heavy applications become more prevalent and complex, the demand for developers to provide reasonably short response times for their users becomes a harder and harder problem to solve. Lots of the algebraically intensive work rests on computer architects, who aim to increase the speed of digital computations at the hardware level. Much of the modern progress in the field of computer architecture has been developed through improving linear algebra calculations, which are ubiquitous in modern computing systems. Despite this, speeding up linear algebra computation remains a significant design problem in modern processors. Our Senior Design project aims to solve this problem by augmenting the functionality of the processor’s data path to save a few calculation cycles which will, over the course of many operations, result in a significant increase the speed of linear algebra computations. Specifically, we have extended the ARMv4 ISA with new instructions that utilize successive data operations to optimize the speed of linear algebra optimizations in a synthesizable RTL Verilog implementation.