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Building Accurate and Error-Tolerant Analog Computing Systems


Location: EER 3.640/3.642
T. Patrick Xiao
Sandia National Laboratories

Analog computing is experiencing a renaissance owing to its promise of high energy efficiency, but to be practical, it must overcome its historical shortcomings in precision. Unlike conventional digital processors, the accuracy of analog in-memory computing systems is directly beset by noise, variability, and myriad other parasitic physical effects. In this talk, we will discuss what the structure of an algorithm tells us about how to design systems whose accuracy is intrinsically more robust to analog errors, or possibly how to leverage analog errors for algorithmic gain. We will present four application algorithms as co-design exemplars: deep neural network inference, the Fourier transform, solving linear systems, and Bayesian neural networks for uncertainty quantification. We use a combination of multi-scale modeling and a large-scale in-memory computing prototype to show how each application should be met by a different approach to the design of the memory device and analog system architecture. In particular, we experimentally show how the device-level properties of subthreshold charge-trap flash memory can leverage the structure of the non-uniform weight distributions in convolutional neural networks to provide robustness. For Bayesian neural networks, we show how stochastic magnetic tunnel junction memories can be used to both store and perform efficient computations with probability distributions.

T. Patrick Xiao is a Senior Member of Technical Staff at Sandia National Laboratories. He received his Bachelor’s in Physics in 2014 and his Ph.D. in Electrical Engineering and Computer Science in 2019, both from the University of California, Berkeley. At Sandia, he is leading projects to develop reliable and energy-efficient analog processors to solve various mission challenges. He also leads the development of multi-scale modeling tools to enable the co-design of devices, circuits, hardware architectures, and algorithms. His research interests include physics-based or analog computing; hardware/software co-design for accurate computing; machine learning accelerators; continuous and combinatorial optimization accelerators; non-volatile memory technologies including flash, spintronics, and memristors; and radiation-hard microelectronics. He has served on the technical committees of the Design Automation and Test in Europe (DATE) conference, the International Conference on Rebooting Computing (ICRC), and was an invited contributor to the International Roadmap for Devices and Systems (IRDS).