Title: From synthesis to detailed routing, with a side of ML: modern challenges in digital implementation.

Abstract: The previous four decades have yielded significant research in digital implementation.  Placement, detailed placement, buffering, wire sizing, Boolean optimization, gate sizing, timing analysis, global routing, clock tree synthesis, are all complex problems that have been heavily researched.  But the key challenges in a modern design flow lies in the interaction of how all these point tools work cohesively as the design move from RTL through the implementation phases down to signoff optimization. The interactions of these components have created areas of research that are relatively unexplored.  In addition, an entirely new paradigm of using machine learning and artificial intelligence to explore the gamut of potential configurations of the digital implementation is changing the way designers approach implementation.  This talk will present an overview of how digital implementation flows work, starting from RTL, going down to detailed routing, and presenting many of the challenges that remain, while also describing how AI/ML is changing the way design is performed, which is opening an exciting new frontier of research in the realm of physical synthesis.

Charles (Chuck) Alpert received a B.S. in Math and Computational Sciences and a B.A. degree in History from Stanford in 1991, and a Ph.D. in Computer Science in 1996 from UCLA.  He then worked for IBM research, focusing on physical design research in placement, buffering, routing and wire synthesis.  In 2014, Chuck joined Cadence Design Systems, where he has worked in many parts of the digital implementation portfolio, managing several teams and projects including logic synthesis, clock tree synthesis, global routing, and most recently running Cerebrus, Cadence’s AI-based Digital Exploration product.  Chuck is an IEEE Fellow and published over 100 papers in leading conferences and journals in electronic design automation. He has received over 100 patents and is a Cadence Master Inventor.  He has also co-edited the Handbook on Physical Design Automation, and has served as deputy editor-in-chief for IEEE Transactions on Computer-Aided Design.  He has also served as general chair for the 2016 IEEE/ACM Design Automation Conference, the Tau and CANDE Workshops, and the ACM International Symposium on Physical Design.