"Bringing RISC-V from Idea to Silicon"

What does it take for an open-source RISC-V core coming out of academia to be used in industry? This talk discusses the technical challenges of evaluating all aspects of a new ISA, processor, and the associated ecosystem of tools.

Talk open to ECE Graduate students only
*Food and Swag will be provided*

Jacob Read does digital modeling, emulation, and performance analysis at Cirrus Logic.  He grew up in Austin and attended UT class of 2019 where he majored in ECE with a focus on Computer Architecture.  Jacob then went on to complete the integrated Master’s program in 2020 with the same focus.  At UT he participated in Longhorn Brazilian Jiu Jitsu, Hillhouse Student Fellowship, HKN, and student government as one of the engineering representatives.  Now he lives in South Austin and enjoys working downtown where he can go from the office to standup paddleboarding in 10 minutes.